With the advance of the semiconductor manufacturing technology, more and more devices are integrated into a semiconductor circuit. Through-Silicon-Vias (TSV) extend all the way through the substrate so that electrical connections can be made from one major planar side of the substrate, perpendicularly through the substrate, and to an opposite major planar side of the substrate. Conventional TSVs are generally copper vias extending through the substrate of a semiconductor chip. The copper via structure is laterally electrically isolated from the substrate by a silicon oxide dielectric liner, and etched into a bulk substrate to a predetermined depth (e.g., 40 μm). The remainder bulk semiconductor below the bottom of the TSV can be utilized as a seed for epitaxial semiconductor or ultimately to be polished away.
TSVs are known to be suitable for high speed signal transmission in structures such as e.g., in an interposer or in a silicon circuit board.
A TSV structure generally includes a metal strip portion that extends through a relatively long and relatively small diameter hole. A method of forming the TSV structure starts with a substrate layer having a hole. A cylindrical metal sheath lines up within the cylindrical sidewall surface of the hole. The substrate layer preferably includes a layer of mono-crystalline semiconductor material having a first major surface disposed in a first plane, and a second major surface disposed in a second plane, where the first and second planes are parallel to one another and are generally separated by more than 75 microns. The hole typically has a small diameter hole, usually less than 100 microns.
Referring to FIG. 1A, a conventional TSV is shown having a metal pad contact 113 covering the entire top surface of the TSV, typically utilized in a C-V measurement with terminals determined by the contacted TSV top surface, illustrated by a cross-sectional plane 116 and surrounded by silicon substrate 120. The resulting measurement is sensitive to leakage and oxide variation in a large area consisting of an annular shaped TSV 112 surrounded by the TSV dielectric liner 111 and substrate 120.
Referring to FIG. 1B, a top-down cross-sectional plane 106 is shown framing the conventional TSV 112 embedded within substrate 120. The substrate can be made of Si, GE, SiAs, silicon-germanium alloy, and the like. The substrate is depicted having a top metal layer 113 embedded in dielectric fill 119. The TSV is further shown surrounded by dielectric liner 111. The region of the TSV surrounded by dielectric liner 111 is referred to as the core of the TSV, the core 131 filled with dielectric resting on the substrate.
Still referring to FIGS. 1A and 1B, the TSV structure is illustrated having an inner and an outer region of the substrate, the regions separated by TSV 112 annulus. The semiconducting material of substrate 120 within the TSV annulus is isolated from the semiconducting material substrate within the exterior of the TSV. The two regions communicate electrically only by way of the semiconducting material substrate 120 surrounding the bottom surface of the TSV annulus along the entirety of the annulus bottom surface. Therefore, the deeper the TSV, the longer is the bottom surface of the TSV 112, as shown in the cross-sectional view of FIG. 1A. Electrical current flowing through the semiconducting material substrate 120 connecting the inner and outer regions will therefore decrease as the bottom surface of the TSV becomes longer, or conversely the TSV becomes deeper while keeping all the remaining electrical parameters constant for comparison. Additionally, the electrical current varies when the TSV 112 metal electrical potential changes.
Conventional TSVs are generally unable to characterize the integrity of the TSV dielectric liner 111, particularly when the TSV dielectric liner is physically cracked, causing an increase in the flow of electrical current between the TSV 112 metal and the surrounding semiconducting material of substrate 120, which should normally be electrically isolated from each other for optimal use.
The previously described problem is further amplified by having the electrical channel surrounding the entire bottom surface of the TSV via the annulus. Any crack anywhere on the bottom surface can create sufficient electrical current leakage between the TSV 112 metal and either one of the inner or outer TSV regions.
A further problem can be created by the inability to interrogate the integrity of the TSV dielectric liner 111 by detecting copper metal that diffuses out of the TSV via annulus. The copper metal generally degrades the semiconducting properties of the channels.
In summary, the electrical measurements of capacitance generally do not cover the entire depth of the TSV and are therefore of limited use when charactering the overall integrity of the TSV liner. The liner can have a varying thickness along its depth, and can crack at different spots of its surface, or cannot block diffusion of copper from the TSV metal to the semiconducting material surrounding the TSV. Moreover, copper contamination of the semiconducting material surrounding the TSV can degrade the performance of devices in circuits outside the TSV.
Accordingly, it would be desirable to create a structure and a method of manufacturing the same making contact to the TSV core using an epitaxial layer and an annular TSV forming an FET, particularly when the FET is U-shaped. The desired structure should further be capable to provide a characterization to overcomes the limitations with other characterization structures and complement them, and further to make it possible to determine the integrity of the TSV dielectric liner.